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? semiconductor components industries, llc, 2006 january, 2006 ? rev. 1 1 publication order number: NB7L216/d NB7L216 2.5v/3.3v, 12gb/s multi level clock/data input to rsecl, high gain receiver/buffer/translator with internal termination description the NB7L216 is a dif ferential receiver/driver with high gain output targeted for high frequency applications. the device is functionally equivalent to the nbsg16 but with much higher gain output. this highly versatile device provides 35 db of gain up to 7 ghz. inputs incorporate internal 50 termination resistors and accept negative ecl (necl), positive ecl (pecl), lvttl, lvcmos, cml, or lvds. outputs are reduced swing ecl (rsecl), 400 mv. the v bb pin is internally generated voltage supply available to this device only. the v bb is used as a reference voltage for single ? ended necl or pecl inputs. for all single ? ended input conditions, the unused complementary differential input should be connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb output should be left open. application notes, models and support documentation are available at www.onsemi.com. features ? high gain of 35 db from dc to 7 ghz typical ? high iip3: 0 db typical ? 20 mv minimum input voltage swing ? maximum input clock frequency up to 8.5 ghz ? maximum input data rate up to 12 gb/s typical ? <0.5 ps of rms clock jitter ? <9 ps of data dependent jitter ? 120 ps typical propagation delay ? 30 ps typical rise and fall times ? rspecl output with operating range: v cc = 2.375 v to 3.465 v with v ee = 0 v ? rsnecl output with rsnecl or necl inputs with operating range: v cc = 0 v with v ee = ? 2.375 v to ? 3.465 v ? rsecl output level (400 mv peak ? to ? peak output), ? 50 internal input termination resistors (temperature ? coefficient of < 6.38 m / c) ? v bb ? ecl reference voltage output ? pb ? free packages are available 50 50 vtd d d vtd q q qfn ? 16 mn suffix case 485g marking diagram * *for additional marking information, refer to application note and8002/d. a = assembly location l = wafer lot y = year w = work week = pb ? free package see detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. ordering information 16 nb7l 216 alyw 1 figure 1. functional block diagram time (17 ps/div) figure 2. typical output waveform at 12 gb/s with prbs 2 23 ? 1 (v inpp = 400 mv, input signal ddj = 12 ps) voltage (60 mv/div) http://onsemi.com device ddj = 3 ps (note: microdot may be in either location)
NB7L216 http://onsemi.com 2 v ee v ee v bb v ee v ee v cc q q v cc vtd d d vtd 5678 16 15 14 13 12 11 10 9 1 2 3 4 NB7L216 exposed pad (ep) figure 3. qfn ? 16 pinout (top view) v ee v ee v ee table 1. pin description pin name i/o description 1 vtd ? internal 50 termination pin. see table 7. note 1 2 d lvpecl, cml, lvcmos, lvds, lvttl input inverted differential input. note 1. 3 d lvpecl, cml, lvcmos, lvds, lvttl input noninverted differential input. note 1. 4 vtd ? internal 50 termination pin. see table 7. note 1. 15 v bb ? internally generated ecl reference voltage supply. 5, 6, 7, 8, 13, 14, 15 v ee ? negative supply voltage. all v ee pins must be externally connected to power supply to guarantee proper operation. 9, 12 v cc ? positive supply voltage. all v cc pins must be externally connected to power supply to guarantee proper operation 10 q rsecl output noninverted differential output. typically receiver terminated with 50 resistor to v tt = v cc ? 2.0 v. 11 q rsecl output inverted differential output. typically receiver terminated with 50 resistor to v tt = v cc ? 2.0 v. ? ep ? exposed pad (ep). thermally exposed pad on the package bottom must be attached to a heat sinking conduit. it is recommended to connect the ep to the lower potential, v ee . 1. in the dif ferential configuration when the input termination pins (vtd, vtd ) are connected to a common termination voltage and if no signal is applied on d/d input then the device will be susceptible to self ? oscillation.
NB7L216 http://onsemi.com 3 table 2. attributes characteristics value esd protection human body model machine model charged device model > 500 kv > 50 v > 4 kv moisture sensitivity (note 2) pb pkg pb ? free pkg qfn ? 16 level 1 level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 164 meets or exceeds jedec spec eia/jesd78 ic latchup test. 2. for additional information, see application note and8003/d. table 3. maximum ratings (note 3) symbol parameter condition 1 condition 2 rating unit v cc positive power supply v ee = 0 v 3.6 v v ee negative power supply v cc = 0 v ? 3.6 v v i positive input negative input v ee = 0 v v cc = 0 v v i = v cc v i = v ee 3.6 ? 3.6 v v v inpp differential input voltage |d ? d | 2.8 v i in input current through r t (50 resistor) static surge 45 80 ma ma i out output current continuous surge 25 50 ma ma i bb v bb sink/source 0.5 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 4) 0 lfpm 500 lfpm qfn ? 16 qfn ? 16 42 35 c/w c/w jc thermal resistance (junction ? to ? case) 1s2p (note 4) qfn ? 16 4 c/w t sol wave solder pb pb ? free 265 265 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. 3. maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. if stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected. 4. jedec standard multilayer board ? 1s2p (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
NB7L216 http://onsemi.com 4 table 4. dc characteristics, clock inputs, cml outputs v cc = 2.375 v to 3.465 v, v ee = 0 v symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max i ee power supply current (vtd/vtd open) 27 35 27 35 27 35 ma v oh output high voltage (note 5 and 6) v cc ? 1040 v cc ? 980 v cc ? 940 v cc ? 1000 v cc ? 950 v cc ? 900 v cc ?950 v cc ? 900 v cc ? 850 mv v ol output low voltage (note 5 and 6) v cc ? 1520 v cc ? 1430 v cc ? 1320 v cc ? 1470 v cc ? 1370 v cc ? 1270 v cc ?1440 v cc ? 1340 v cc ? 1240 mv differential input driven single ? ended (see figures 14 and 16) v th input threshold reference voltage range (note 7 and 8) 1100 v cc ? 10 1100 v cc ? 10 1100 v cc ? 10 mv v ih single ? ended input high voltage (note 8) v th +10 v cc v th + 10 v cc v th +10 v cc mv v il single ? ended input low voltage (note 8) v ee v th ? 10 v ee v th ? 10 v ee v th ? 10 mv differential inputs driven differentially (see figures 15 and 17) v ihd differential input high voltage (note 9) 1105 v cc 1105 v cc 1105 v cc mv v ild differential input low voltage (note 9) v ee v cc ? 10 v ee v cc ? 10 v ee v cc ? 10 mv v cmr input common mode range (differential configuration, note 9 and 10) 1100 v cc ? 5 1100 v cc ?5 1100 v cc ?5 mv v id differential input voltage (v ihd ? v ild ) 10 2500 10 2500 10 2500 mv v io input offset voltage (note 11) ? 5 0 +5 ? 5 0 +5 ? 5 0 +5 mv v bb internally generated reference voltage supply (only 3 v ? 3.6 v supply load with ? 100 a) v cc ? 1425 v cc ? 1345 v cc ? 1265 v cc ? 1425 v cc ? 1345 v cc ? 1265 v cc ? 1425 v cc ? 1345 v cc ? 1265 mv i ih input high current d/db (vtd/vtd open) 0 20 100 0 20 100 0 20 100 a i il input low current d/db (vtd/vtd open) ? 25 10 75 ? 25 10 75 ? 25 10 75 a r tin internal input termination resistor 45 50 55 45 50 55 45 50 55 r t_coef internal input termination resistor temperature coefficient 6.38 6.38 6.38 m / c note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit val ues are applied individually under normal operating conditions and not valid simultaneously. 5. outputs evaluated with 50 resistors to v tt = v cc ? 2.0 v for proper operation. 6. input and output parameters vary 1:1 with v cc . 7. v th is applied to the complementary input when operating in single ? ended mode. 8. v ih , v il and v th parameters must be complied simultaneously. 9. v ihd , v ild and v cmr parameters must be complied simultaneously. 10. v cmr min varies 1:1 with v ee , v cmr max varies 1:1 with v cc . 11. typical standard deviation of input offset voltage is 1.76 mv.
NB7L216 http://onsemi.com 5 table 5. ac characteristics v cc = 2.375 v to 3.465 v, v ee = 0 v; (note 12) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max v outpp output voltage amplitude (@ v inppmin )f in 7.0 ghz (see figure 4) f in 8.5 ghz 275 100 380 250 275 100 380 250 275 100 380 250 mv f data maximum operating data rate 10 12 10 12 10 12 gb/s |s21| power gain dc to 7 ghz 35 35 35 db |s11| input return loss @ 7 ghz ? 10 ? 10 ? 10 db |s22| output return loss @ 7 ghz ? 5 ? 5 ? 5 db |s12| reverse isolation (differential configuration) ? 25 ? 25 ? 25 db iip3 input third order intercept 0 0 0 dbm t plh , t phl propagation delay to output differential @ 1 ghz 60 120 180 60 120 180 60 120 180 ps t skew duty cycle skew (note 12) device to device skew (note 17) 2 5 10 20 2 5 10 20 2 5 10 20 ps t jitter rms random clock jitter f in 8.5 ghz (note 15) peak ? to ? peak data dependent jitter (note 16) f data = 3.5 gb/s f data = 5.0 gb/s f data = 10 gb/s f data = 12 gb/s 0.1 1 3 4 4 0.5 7 9 9 9 0.1 1 3 4 4 0.5 7 9 9 9 0.1 1 3 4 4 0.5 7 9 9 9 ps v inpp input voltage swing/sensitivity (differential configuration) (note 14 and figure 12) 20 2500 20 2500 20 2500 mv t r t f output rise/fall times @ 0.5 ghz q, q (20% ? 80%) 30 45 30 45 30 45 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit val ues are applied individually under normal operating conditions and not valid simultaneously. 12. measured by forcing v inppmin from a 50% duty cycle clock source. all loading with an external r l = 50 to v tt =v cc ? 2.0 v. input edge rates 40 ps (20% ? 80%). 13. duty cycle skew is measured between differential outputs using the deviations of the sum of tpw ? and tpw+ @ 1 ghz. 14. v inpp (max) cannot exceed v cc ? v ee . input voltage swing is a single ? ended measurement operating in differential mode. 15. additive rms jitter with 50% duty cycle clock signal. 16. additive peak ? to ? peak data dependent jitter with input nrz data at prbs 2 23 ? 1. 17. device to device skew is measured between outputs under identical transition @ 1 ghz. 0 50 100 150 200 250 300 350 400 450 500 246789101112 0 figure 4. output voltage amplitude (v outpp ) versus input clock frequency (f in ) and temperature (v inpp = 400 mv, v cc = 3.3 v and v ee = 0 v) 25 c ? 40 c 85 c input clock frequency (ghz) output voltage amplitude (mv) 0 50 100 150 200 250 300 350 400 450 500 246789101112 0 ? 40 c 25 c 85 c input clock frequency (ghz) output voltage amplitude (mv) figure 5. output voltage amplitude (v outpp ) versus input clock frequency (f in ) and temperature (v inpp = 20 mv, v cc = 3.3 v and v ee = 0 v)
NB7L216 http://onsemi.com 6 time (66 ps/div) figure 6. typical output waveform at 2.488 gb/s with prbs 2 23 ? 1 (v inpp = 400 mv, input signal ddj = 12 ps) voltage (60 mv/div) time (54 ps/div) figure 7. typical output waveform at 3.5 gb/s with prbs 2 23 ? 1 (v inpp = 400 mv, input signal ddj = 12 ps) voltage (60 mv/div) voltage (60 mv/div) time (37 ps/div) figure 8. typical output waveform at 5 gb/s with prbs 2 23 ? 1 (v inpp = 400 mv, input signal ddj = 12 ps) time (21 ps/div) figure 9. typical output waveform at 10 gb/s with prbs 2 23 ? 1 (v inpp = 400 mv, input signal ddj = 12 ps) voltage (60 mv/div) device ddj = 1 ps device ddj =1 ps device ddj =2 ps device ddj = 3 ps frequency (ghz) gain (db) 0 5 10 15 20 25 30 35 40 figure 10. small signal gain ? s21 magnitude* ? 50 ? 40 ? 30 ? 20 ? 10 0 gain (db) frequency (ghz) figure 11. input and output reflection ? s11 and s22 magnitude* 0 s11 s22 2 4 6 8 10 12 14 16 02 46 8 10121416 *t a = +25 c, v cc = 3.3 v, v ee =0 v, p in = ? 44 dbm,z s = z l = 50 , input and output matching network is not included.
NB7L216 http://onsemi.com 7 table 6. typical device s ? parameters frequency (hz) s11 s21 s12 s22 dbs11 |s11| s11 dbs21 |s21| s21 dbs12 |s12| s12 dbs22 |s22| s22 4.97e+08 ? 45.2 0.005 ? 88.5 37.2 72.799 ? 33.2 ? 72.3 0.001 ? 139.1 ? 2.5 0.749 157.4 1.02e+09 ? 30.4 0.030 ? 134.7 37.3 73.145 ? 68.4 ? 45.8 0.005 129.8 ? 2.9 0.714 154.3 1.51e+09 ? 36.2 0.015 ? 146.5 37.1 71.433 ? 105.4 ? 43.3 0.007 98.5 ? 2.9 0.717 132.8 2.00e+09 ? 27.4 0.042 25.7 37.4 74.061 ? 139.0 ? 37.1 0.014 91.8 ? 3.5 0.666 107.1 2.52e+09 ? 12.3 0.244 ? 27.7 36.2 64.810 ? 179.5 ? 29.9 0.032 54.4 ? 4.4 0.599 92.1 3.01e+09 ? 10.6 0.295 ? 83.8 36.9 70.102 144.5 ? 26.1 0.050 9.4 ? 6.3 0.485 77.3 3.50e+09 ? 19.0 0.112 ? 22.1 35.4 58.933 99.9 ? 28.3 0.038 25.9 ? 5.0 0.566 67.9 4.02e+09 ? 10.6 0.294 ? 120.3 35.6 60.437 73.8 ? 24.8 0.058 ? 32.6 ? 7.6 0.417 54.2 4.51e+09 ? 10.7 0.291 167.4 36.0 62.843 41.1 ? 22.5 0.075 ? 68.3 ? 13.9 0.201 70.2 4.99e+09 ? 9.0 0.354 87.1 35.1 56.576 14.2 ? 25.2 0.055 ? 107.2 ? 8.7 0.367 81.2 5.48e+09 ? 10.6 0.294 62.7 36.4 65.812 ? 16.1 ? 24.3 0.061 ? 121.4 ? 8.0 0.398 50.4 6.01e+09 ? 9.3 0.341 108.2 35.8 61.327 ? 72.8 ? 24.5 0.060 ? 125.7 ? 8.0 0.397 ? 0.9 6.49e+09 ? 9.4 0.340 59.4 36.2 64.212 ? 119.4 ? 21.9 0.080 ? 152.4 ? 12.5 0.237 ? 27.2 6.98e+09 ? 17.5 0.133 25.5 34.3 52.039 ? 141.5 ? 22.7 0.073 177.5 ? 7.4 0.428 ? 32.2 7.51e+09 ? 25.6 0.053 107.9 33.2 45.861 164.6 ? 24.4 0.060 165.7 ? 7.0 0.445 ? 37.9 7.99e+09 ? 13.7 0.206 146.5 25.2 18.093 133.6 ? 21.5 0.084 152.8 ? 7.6 0.416 ? 54.7 8.52e+09 ? 6.7 0.462 117.9 22.6 13.434 116.2 ? 19.4 0.107 120.7 ? 12.1 0.249 ? 73.7 9.00e+09 ? 5.2 0.552 106.2 19.4 9.336 102.0 ? 19.0 0.112 109.9 ? 12.2 0.246 ? 62.5 9.49e+09 ? 3.7 0.652 71.1 19.0 8.937 61.1 ? 19.4 0.107 62.0 ? 11.5 0.267 ? 100.2 1.00e+10 ? 9.7 0.326 46.2 18.7 8.595 18.6 ? 24.0 0.063 50.6 ? 10.4 0.301 ? 117.0 1.05e+10 ? 11.0 0.283 35.8 14.5 5.298 ? 13.3 ? 25.9 0.051 12.9 ? 10.8 0.288 ? 172.0 1.10e+10 ? 8.3 0.384 7.2 12.9 4.408 ? 9.6 ? 29.4 0.034 21.1 ? 13.4 0.213 74.0 1.15e+10 ? 5.9 0.506 ? 0.4 12.7 4.339 ? 33.7 ? 21.4 0.085 36.3 ? 21.4 0.085 ? 148.6 1.20e+10 ? 9.0 0.356 ? 23.8 12.9 4.395 ? 63.4 ? 19.4 0.107 ? 9.5 ? 13.4 0.214 159.5 1.25e+10 ? 15.6 0.166 ? 46.9 10.5 3.360 ? 97.8 ? 21.0 0.089 ? 39.0 ? 12.4 0.239 169.2 1.30e+10 ? 15.1 0.175 ? 83.0 9.9 3.121 ? 119.7 ? 24.0 0.063 ? 39.9 ? 11.3 0.272 171.6 1.35e+10 ? 12.0 0.250 ? 96.5 8.7 2.728 ? 148.9 ? 22.0 0.079 ? 39.1 ? 14.9 0.181 177.8 1.40e+10 ? 11.5 0.265 ? 105.9 7.3 2.314 ? 167.1 ? 18.6 0.118 ? 74.2 ? 18.4 0.120 140.3 1.45e+10 ? 17.0 0.140 ? 97.8 5.4 1.856 167.6 ? 20.1 0.099 ? 107.0 ? 15.7 0.163 98.2 1.50e+10 ? 23.4 0.068 ? 108.9 4.6 1.695 145.0 ? 20.2 0.098 ? 128.1 ? 11.2 0.274 96.1 note: t a = +25 c, v cc =3.3v, v ee = 0 v, p in = ? 44 dbm, z s = z l = 50 , input and output matching network is not included.
NB7L216 http://onsemi.com 8 figure 12. ac reference measurement d d q q t phl t plh v inpp = v ih (d) ? v il (d) v outpp = v oh (q) ? v ol (q) figure 13. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v figure 14. differential input driven single ? ended figure 15. differential inputs driven differentially figure 16. v th diagram figure 17. v cmr diagram d v cc gnd v ih v ihmin v ihmax v thmax v th v th v thmin v cmmax v cmmax d v cmr v cc gnd d d v th v th d d v ilmax v il v ilmin d v ildmax v ihdmax v id = v ihd ? v ild v ildtyp v ihdtyp v ildmin v ihdmin note: v ee v in v cc ; v ih > v il
NB7L216 http://onsemi.com 9 application information all NB7L216 inputs can accept pecl, cml, lvttl, lvcmos and lvds signal levels. the limitations for differential input signal (lvds, pecl, or cml) are minimum input swing of 75 mv and the maximum input swing of 2500 mv . within these conditions, the input voltage can range from v cc to 1.2 v. examples interfaces are illustrated below in a 50 environment (z = 50 ). for output termination and interface, refer to application note and8020/d. table 7. interfacing options interfacing options connections cml connect vtd and vtd to v cc (see figure 18) lvds connect vtd and vtd together (see figure 20) ac ? coupled bias vtd and vtd inputs within common mode range (v cmr ) (see figure 19) rsecl, pecl, necl standard ecl termination techniques (see figure 13) lvttl, lvcmos an external voltage (v thr ) should be applied to the unused complementary differential input. nominal v thr is 1.5 v for lvttl and v cc / 2 for lvcmos inputs. this voltage must be within the v thr specification. (see figure 21) 50 v cc d d 50 NB7L216 v cc vtd v ee v cc q 50 50 cml driver v ee figure 18. cml to NB7L216 interface q z = 50 figure 19. pecl to NB7L216 interface 50 v cc v cc pecl driver d d 50 NB7L216 v ee v bias * vtd v ee r t r t v ee v cc r t 5.0 v 290 3.3 v 150 2.5 v 80 recommended r t values vtd v cc vtd v bias * z = 50 z = 50 z = 50 c c *v bias must be within common mode range limits (v cmr )
NB7L216 http://onsemi.com 10 50 v cc v cc lvds driver d d 50 NB7L216 v ee vtd v ee vtd figure 20. lvds to NB7L216 interface figure 21. lvcmos/lvttl to NB7L216 interface 50 v cc v cc lvttl/ lvcmos driver d d 50 NB7L216 v ee vtd v cc v ref lvcmos v cc ? v ee 2 lvttl 1.5 v recommended v ref values vtd v ref no connect* no connect *or 60 pf to gnd z = 50 z = 50 z = 50
NB7L216 http://onsemi.com 11 ordering information device package shipping ? NB7L216mn qfn ? 16 123 units / rail NB7L216mng qfn ? 16 (pb ? free) 123 units / rail NB7L216mnr2 qfn ? 16 3000 / tape & reel NB7L216mnr2g qfn ? 16 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NB7L216 http://onsemi.com 12 package dimensions 16 pin qfn case 485g ? 01 issue b 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. l max condition can not violate 0.2 mm minimum spacing between lead tip and flag ??? ??? ??? b a 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c 16 x e 16x note 5 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k 0.20 ??? l 0.30 0.50 exposed pad mm inches scale 10:1 0.50 0.02 0.575 0.022 1.50 0.059 3.25 0.128 0.30 0.012 3.25 0.128 0.30 0.012 exposed pad *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 NB7L216/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082 ? 1312 usa phone : 480 ? 829 ? 7710 or 800 ? 344 ? 3860 toll free usa/canada fax : 480 ? 829 ? 7709 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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